1. Field of the Invention
This invention relates generally to computer signal communication, and more particularly to an integrated circuit interface and method for high speed block transfer signaling of data, control and address signals between multiple integrated circuits on a bus or point-to-point with reduced power consumption.
2. Description of the Background Art
Semiconductor integrated circuits used in digital computing and other digital applications often use a plurality of Very Large Scale Integration (VLSI) interconnected circuits for implementing binary communication across single or multi-segmented transmission lines. Conventional transmission lines include traces, which are formed on a suitable substrate, such as a printed circuit board. Each transmission line may be designed, for example, using so-called micro-strip traces and strip line traces to form a transmission line having a characteristic impedance on the order of about 50-70 ohms. Alternatively, each transmission line may have its opposite ends terminated in their characteristic impedance. The output load on a driver for such a transmission line may be as low as 25-35 ohms.
To consume reasonable power, high frequency signaling requires small amplitude signals. For a receiver to detect voltage swings (e.g., 0.8 v to 1.2 v) easily in a noisy environment like GTL, HSTL, SSTL or RAMBUS, the current must also be very large (e.g., on the order of 50 to 60 milliamps per driver). A typical receiver uses a comparator with a voltage reference (VREF) signal configured midway between input high voltage (VIH) and input low voltage (VIL). The VREF signal is a high impedance DC voltage reference which tracks loosely with power supplies over time, but cannot respond to instantaneous noise. Conventionally, High Output Voltage (VOH) and Low Output Voltage (VOL) denote signals emerging from the transmitting source, and VIL and VIH denote signals arriving at the input of the receiving device, although they can be considered the same signal.
FIG. 1A is a block diagram illustrating a prior art receiver 10 using RAMBUS technology. The system 10 includes a pad 100 coupled via signal lines 103 to internal input receivers 110. A VREF signal 105 is coupled to each internal receiver 110. VREF is generated from the power supply. Usually, the DC value of the power supply varies by five percent (5%). FIG. 1B is a timing diagram 125 illustrating an example signal relative to a high reference voltage (VREFh) and a low reference voltage (VREFl). The VREFh and VREFl values typically depend on power supply variation used to generate the VREF signal. The large voltage swing, i.e., the difference between a high voltage signal (VIH) and a low voltage signal (VIL), and stable signal levels above and below the VREF signal are required for reliable detection of signal polarity. The voltage swing of current single-ended signaling technologies is conventionally around 0.8 v.
FIG. 1C is a block diagram illustrating schematics of a prior art receiver 150 using RAMBUS technology. The receiver 150 samples the level of input signal 167 and of the VREF signal 154 until the signal reaches a stable level, at which time the pass gates 160 and 165 turn off. Once the pass gates 160 and 165 turn off, the sense gate 172 is enabled to eliminate current injection. FIG. 1D is a timing diagram 175 illustrating operation of the receiver 150 for an example signal. The receiver 150 samples the input reference and input signal until the signal reaches a stable level, e.g., a low logic level (VIL), and, while the input signal is stable, the receiver 150 senses the value of the input signal. As stated above, for reliable signal detection, the signal voltage swing must be fast enough to allow all the receivers 150 to sample a stable signal with an adequate margin for set-up and hold time. This voltage swing should occur in less than 30% of the minimum cycle time to allow margin for signal skew, set-up and hold-times. As the minimum cycle time reduces below 1 nanosecond, the margins reduce for signal skew, set-up time and hold-time, with the additional burden on the driver current in a high capacitance loading environment operating at high frequency. Low voltage differential signaling (LVDS) used by IEEE P1596.3 can overcome these problems by using a 250 mv voltage swing at the expense of running complimentary signals. Running complementary signals inevitably increases the pin count and package size.
Further, computer systems typically utilize a bus system in which several devices are coupled to the bus. Most of them use a clock to validate data, address and control signals. FIG. 21 illustrates a prior art system 2100 for DRDRAM, which uses a clock line 2130 having two segments 2136 and 2138. One segment 2136 extends from one end of the data bus to a turnaround point 2137 near the second end of the bus. The other clock segment 2138 extends from the turnaround 2137 back to the first end of the data bus. The signal bus 2120 carries data, address and control signals. This topology ensures that a signal sent on the bus 2120 always travels contemporaneously with and in the same direction as the clock 2132 used by the device to receive the signal. This works fine if the loading off all signals and the clock is almost identical and the clock 2132 is used to sample and receive the signal. However, sometimes the system might require twice the data bandwidth in which case this type of bus system needs to double the number of signals even though the address and control signals are identical, and could have been shared.
Accordingly, there is a need for low power drivers and reliable receivers for high frequency operation of a large number of single-ended signals in existing technology for low cost VLSI digital systems.